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This commit is contained in:
Andrew Pamment 2021-11-26 21:06:12 +10:00
parent 35876591d5
commit 0d5c86649b
1 changed files with 16 additions and 16 deletions
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32
i825xx.c
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@ -341,20 +341,20 @@ struct ether_t *init_i825xx(int count) {
i825xx_dev->rx_desc[i]->status = 0;
}
mmio_write(REG_TDBAL, (unsigned int)((unsigned long long)ptr >> 32));
mmio_write(REG_TDBAH, (unsigned int)((unsigned long long)ptr & 0xFFFFFFFF));
mmio_write(i825xx_dev, REG_TDBAL, (unsigned int)((unsigned long long)ptr >> 32));
mmio_write(i825xx_dev, REG_TDBAH, (unsigned int)((unsigned long long)ptr & 0xFFFFFFFF));
mmio_write(REG_RDBAL, (unsigned long long)ptr);
mmio_write(REG_RDBAH, 0);
mmio_write(i825xx_dev, REG_RDBAL, (unsigned long long)ptr);
mmio_write(i825xx_dev, REG_RDBAH, 0);
mmio_write(REG_RDLEN, NUM_RX_DESCRIPTORS * 16);
mmio_write(i825xx_dev, REG_RDLEN, NUM_RX_DESCRIPTORS * 16);
mmio_write(REG_RDH, 0);
mmio_write(REG_RDT, NUM_RX_DESCRIPTORS - 1);
mmio_write(i825xx_dev, REG_RDH, 0);
mmio_write(i825xx_dev, REG_RDT, NUM_RX_DESCRIPTORS - 1);
i825xx_dev->rx_front = 0;
mmio_write(REG_RCTRL, RCTL_SBP| RCTL_UPE | RCTL_MPE | RCTL_LBM_OFF | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
mmio_write(i825xx_dev, REG_RCTRL, RCTL_SBP| RCTL_UPE | RCTL_MPE | RCTL_LBM_OFF | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
pagesrx = mem_alloc_pages((NUM_TX_DESCRIPTORS * sizeof(struct i825xx_tx_desc_t) + 16) / PAGE_SIZE);
ptr = mem_pci_sbrk(NUM_TX_DESCRIPTORS * sizeof(struct i825xx_tx_desc_t) + 16);
@ -369,27 +369,27 @@ struct ether_t *init_i825xx(int count) {
tx_descs[i]->status = TX_DESC_STATUS_DD;
}
mmio_write(REG_TDBAH, (unsigned int)((unsigned long long)ptr >> 32) );
mmio_write(REG_TDBAL, (unsigned int)((unsigned long long)ptr & 0xFFFFFFFF));
mmio_write(i825xx_dev, REG_TDBAH, (unsigned int)((unsigned long long)ptr >> 32) );
mmio_write(i825xx_dev, REG_TDBAL, (unsigned int)((unsigned long long)ptr & 0xFFFFFFFF));
//now setup total length of descriptors
mmio_write(REG_TDLEN, NUM_TX_DESCRIPTORS * 16);
mmio_write(i825xx_dev, REG_TDLEN, NUM_TX_DESCRIPTORS * 16);
//setup numbers
mmio_write( REG_TDH, 0);
mmio_write( REG_TDT, 0);
mmio_write(i825xx_dev, REG_TDH, 0);
mmio_write(i825xx_dev, REG_TDT, 0);
i825xx_dev->tx_front = 0;
mmio_write(REG_TCTRL, (15 << TCTL_CT_SHIFT)
mmio_write(i825xx_dev, REG_TCTRL, (15 << TCTL_CT_SHIFT)
| (64 << TCTL_COLD_SHIFT)
| TCTL_RTLC);
// This line of code overrides the one before it but I left both to highlight that the previous one works with e1000 cards, but for the e1000e cards
// you should set the TCTRL register as follows. For detailed description of each bit, please refer to the Intel Manual.
// In the case of I217 and 82577LM packets will not be sent if the TCTRL is not configured using the following bits.
mmio_write(REG_TCTRL, 0b0110000000000111111000011111010);
mmio_write(REG_TIPG, 0x0060200A);
mmio_write(i825xx_dev, REG_TCTRL, 0b0110000000000111111000011111010);
mmio_write(i825xx_dev, REG_TIPG, 0x0060200A);
if (!irq_install_handler(pci_dev->irq, i825xx_isr, 0)) {