434 lines
15 KiB
C
434 lines
15 KiB
C
/* This file is a heavily modified version of Joshua Cornutt's intel driver
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* the original license can be found following...
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*/
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/*
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* Copyright (c) 2011 Joshua Cornutt <jcornutt@randomaccessit.com>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "i825xx.h"
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#include "ether.h"
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#include "pci.h"
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#include "console.h"
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#include "string.h"
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#include "memory.h"
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#include "interrupts.h"
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#include "io.h"
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extern struct ether_t **etherdevs;
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extern unsigned int etherdev_count;
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//Registers
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#define REG_CTRL 0x00000 //Control Register
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#define REG_STATUS 0x00008 //Status Register
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#define REG_EERD 0x00014 //EEPROM Read Register
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#define REG_ICR 0x000C0 //Interrupt Cause Read Register
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#define REG_IMS 0x000D0 //Interrupt Mask Set Register
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#define REG_RCTL 0x00100 //Recieve Control Register
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#define REG_TCTL 0x00400 //Transmit Control Register
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#define REG_RDBAL 0x02800 //Recieve Descriptor Base Address Low Register
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#define REG_RDBAH 0x02804 //Recieve Descriptor Base Address High Register
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#define REG_RDLEN 0x02808 //Recieve Descriptor Ring buff Length (bytes) Register
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#define REG_RDH 0x02810 //Recieve Descriptor Head Register
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#define REG_RDT 0x02818 //Recieve Descriptor Tail Register
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#define REG_TDBAL 0x03800 //Recieve Descriptor Base Address Low Register
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#define REG_TDBAH 0x03804 //Recieve Descriptor Base Address High Register
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#define REG_TDLEN 0x03808 //Recieve Descriptor Ring buff Length (bytes) Register
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#define REG_TDH 0x03810 //Recieve Descriptor Head Register
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#define REG_TDT 0x03818 //Recieve Descriptor Tail Register
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#define REG_TIPG 0x0410
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#define REG_MTA 0x05200 //Multicast Table Array Register
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#define REG_RAL 0x05400 //Receive Address Low (MAC filter) Register
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#define REG_RAH 0x05404 //Receive Address High (MAC filter) Register
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#define REG_LAST 0x1FFFC
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//Control Register Flags
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#define CTRL_FD (1 << 0) //Full-Duplex
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#define CTRL_ASDE (1 << 5) //Auto-Speed Detection Enable
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#define CTRL_SLU (1 << 6) //Set Link Up
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//Status Flags
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#define STATUS_LU (1 << 1) //Link Up Indication
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//EEPROM Register Flags
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#define EERD_START (1 << 0) //Start Read
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#define EERD_DONE (1 << 4) //Read Done
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//Recieve Control Register Flags
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#define RCTL_EN (1 << 1)
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#define RCTL_SBP (1 << 2)
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#define RCTL_UPE (1 << 3)
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#define RCTL_MPE (1 << 4)
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#define RCTL_LPE (1 << 5)
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#define RCTL_BAM (1 << 15)
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#define RCTL_VFE (1 << 18)
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#define RCTL_CFIEN (1 << 19)
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#define RCTL_CFI (1 << 20)
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#define RCTL_DPF (1 << 22)
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#define RCTL_PMCF (1 << 23)
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#define RCTL_BSEX (1 << 25)
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#define RCTL_SECRC (1 << 26)
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#define RCTL_LBM_MASK (~(3 << 6))
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#define RCTL_LBM_OFF (0 << 6)
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#define RCTL_LBM_ON (3 << 6)
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#define RCTL_RDMTS_MASK (~(3 << 8))
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#define RCTL_RDMTS_HALF (0 << 8)
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#define RCTL_RDMTS_QUATER (1 << 8)
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#define RCTL_RDMTS_EIGHTH (2 << 8)
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#define RCTL_MO_MASK (~(3 << 12))
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#define RCTL_MO_SHIFT_ZERO (0 << 12)
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#define RCTL_MO_SHIFT_ONE (1 << 12)
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#define RCTL_MO_SHIFT_TWO (2 << 12)
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#define RCTL_MO_SHIFT_FOUR (3 << 12)
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#define RCTL_BSIZE_MASK (~(3 << 16))
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#define RCTL_BSIZE_2048 (0 << 16)
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#define RCTL_BSIZE_1024 (1 << 16)
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#define RCTL_BSIZE_512 (2 << 16)
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#define RCTL_BSIZE_256 (3 << 16)
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#define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
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#define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
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#define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
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//Transmit Control Register Flags
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#define TCTL_EN (1 << 1)
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#define TCTL_PSP (1 << 3)
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//Interrupt Causes
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#define ICR_TXDW (1 << 0) //Transmit Descriptor Written Back
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#define ICR_TXQE (1 << 1) //Transmit Queue Empty
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#define ICR_LSC (1 << 2) //Link Status Change
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#define ICR_RXSEQ (1 << 3) //Receive Sequence Error
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#define ICR_RXDMT (1 << 4) //Receive Descriptor Minimum Threshold Reached
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#define ICR_RXO (1 << 6) //Receiver Overrun
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#define ICR_RXT (1 << 7) //Receiver Timer Interrupt
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#define ICR_MDAC (1 << 9) //MDI/O Access Complete
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#define ICR_RXCFG (1 << 10) //Receiving /C/ ordered sets
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#define ICR_PHY (1 << 12) //PHY Interrupt
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#define ICR_GPI_ONE (1 << 13) //General Purpose Interrupt (SDP6)
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#define ICR_GPI_TWO (1 << 14) //General Purpose Interrupt (SDP7)
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#define ICR_TXD_LOW (1 << 15) //Transmit Descriptor Low Threshold Hit
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#define ICR_SRPD (1 << 16) //Small Receive Packet Detected
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//RX Descriptor Status Flags
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#define RX_DESC_STATUS_DD (1 << 0) //Descriptor Done
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#define RX_DESC_STATUS_EOP (1 << 1) //End Of Packet
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//TX Descriptor Command Flags
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#define TX_DESC_CMD_EOP (1 << 0) //End Of Packet
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#define TX_DESC_CMD_IFCS (1 << 1) //Insert FCS/CRC
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#define TX_DESC_CMD_RS (1 << 3) //Report Status
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//TX Descriptor Status Flags
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#define TX_DESC_STATUS_DD (1 << 0) //Descriptor Done
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#define PAGE_SIZE 4096
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#define PAGE_MASK (~(0xffffffff << 12))
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static __inline__ unsigned long round_up_to_page(unsigned long addr) {
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if ((addr & PAGE_MASK) != 0) {
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addr &= ~(PAGE_MASK);
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addr += PAGE_SIZE;
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}
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return addr;
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}
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static unsigned int mmio_read(struct i825xx_device_t *net_device, unsigned int reg) {
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if (net_device->bar_type == 0) {
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return *(volatile unsigned int *)(net_device->mmio_address + reg);
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} else {
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outportl(net_device->io_address, reg);
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return inportl(net_device->io_address + 4);
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}
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}
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static void mmio_write(struct i825xx_device_t *net_device, unsigned int reg, unsigned int value) {
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if (net_device->bar_type == 0) {
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*(volatile unsigned int *)(net_device->mmio_address + reg) = value;
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} else {
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outportl(net_device->io_address, reg);
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outportl(net_device->io_address + 4, value);
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}
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}
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static unsigned short net_eeprom_read(struct i825xx_device_t *net_device, unsigned char addr) {
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unsigned int tmp = 0;
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unsigned short data;
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if (net_device->have_eeprom) {
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mmio_write(REG_EERD, (1) | ((unsigned int) (addr) << 8));
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while (!((tmp = mmio_read(REG_EERD)) & (1 << 4)));
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} else {
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mmio_write(REG_EERD, (1) | ((unsigned int) (addr) << 2));
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while (!((tmp = mmio_read(REG_EERD)) & ( 1 << 1)));
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}
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mmio_write(net_device, REG_EERD, EERD_START | (((unsigned int) (addr)) << 8));
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data = (unsigned short)((tmp >> 16) & 0xffff);
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return data;
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}
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static void i825xx_poll(struct i825xx_device_t *i825xx_device) {
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while(i825xx_device->rx_desc[i825xx_device->rx_front].status & RX_DESC_STATUS_DD) {
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unsigned char *pkt = (unsigned char *)i825xx_device->rx_buff[i825xx_device->rx_front];
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unsigned short pktlen = i825xx_device->rx_desc[i825xx_device->rx_front]->length;
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if(!(i825xx_device->rx_desc[i825xx_device->rx_front].status & RX_DESC_STATUS_EOP)) {
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kprintf("825xx - rx: no EOP support, dropping");
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} else if(i825xx_device->rx_desc[i825xx_device->rx_front]->length < 60) {
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kprintf("825xx - rx: short packet (%d bytes)", i825xx_device->rx_desc[i825xx_device->rx_front]->length);
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} else {
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ether_receive(i825xx_device->ether, pkt, pktlen);
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}
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i825xx_device->rx_desc[i825xx_device->rx_front]->status = 0;
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i825xx_device->rx_front = (i825xx_device->rx_front + 1) % NUM_RX_DESCRIPTORS;
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mmio_write(i825xx_device, REG_RDT, i825xx_device->rx_front);
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}
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}
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static void i825xx_isr(struct regs *r) {
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struct i825xx_device_t *i825xx_device;
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int i;
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for (i=0;i<etherdev_count;i++) {
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if (etherdevs[i]->type == 1) {
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i825xx_device = (struct i825xx_device_t *)etherdevs[i]->data;
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unsigned int icr = mmio_read(i825xx_device, REG_ICR);
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if (icr & ICR_LSC) {
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if(mmio_read(i825xx_device, REG_STATUS) & STATUS_LU) {
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etherdevs[i]->state = 1;
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} else {
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etherdevs[i]->state = 0;
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}
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}
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if (icr & ICR_RXT) {
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i825xx_poll(i825xx_device);
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}
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}
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}
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}
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int i825xx_send(struct i825xx_device_t *i825xx_device, char *packet, int len) {
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i825xx_device->tx_desc[i825xx_device->tx_front]->addr = (unsigned long long)packet;
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i825xx_device->tx_desc[i825xx_device->tx_front]->length = len;
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i825xx_device->tx_desc[i825xx_device->tx_front]->cmd = TX_DESC_CMD_EOP | TX_DESC_CMD_IFCS | TX_DESC_CMD_RS;
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i825xx_device->tx_desc[i825xx_device->tx_front]->sta = 0;
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unsigned int old_tx_front = i825xx_device->tx_front;
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i825xx_device->tx_front = (i825xx_device->tx_front + 1) % NUM_TX_DESCRIPTORS;
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mmio_write(i825xx_device, REG_TDT, i825xx_device->tx_front);
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while(!(i825xx_device->tx_desc[old_tx_front]->sta & 0xFF));
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return i825xx_device->tx_desc[old_tx_front]->sta & TX_DESC_STATUS_DD ? 0 : -1;
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}
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unsigned char i825xx_detect_eeprom() {
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unsigned int val = 0;
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unsigned char eeprom_exists = 0;
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mmio_write(REG_EERD, 0x1);
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for (int i = 0; i < 1000 && !eeprom_exists;i++) {
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val = mmio_read(REG_EERD);
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if (val & 0x10) {
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eeprom_exists = 1;
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} else {
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eeprom_exists = 0;
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}
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}
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return eeprom_exists;
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}
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struct ether_t *init_i825xx(int count) {
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struct pci_device *pci_dev;
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struct i825xx_device_t *i825xx_dev;
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struct ether_t *ether_dev;
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unsigned int i;
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unsigned short j;
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if (!pci_find_device_by_vendor(0x8086, 0x100E, &pci_dev, count)) {
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if (!pci_find_device_by_vendor(0x8086, 0x153A, &pci_dev, count)) {
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if (!pci_find_device_by_vendor(0x8086, 0x10EA, &pci_dev, count)) {
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return (void *)0;
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}
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}
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}
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i825xx_dev = (struct i825xx_device_t *)malloc(sizeof(struct i825xx_device_t));
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ether_dev = (struct ether_t *)malloc(sizeof(struct ether_t));
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// if not memory mapped
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if (pci_dev->base[0] & 0x1) {
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i825xx_dev->bar_type = 1;
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unsigned int addr = (pci_dev->base[0] & 0xfffffff0);
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unsigned int size = round_up_to_page(REG_LAST);
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unsigned int mem_space = mem_pci_sbrk(size);
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for (i=0;i<size;i+=PAGE_SIZE) {
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mem_map_page(addr + i, mem_space + i, 3);
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}
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i825xx_dev->mmio_address = mem_space;
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} else {
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i825xx_dev->bar_type = 0;
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i825xx_dev->io_address = pci_dev->base[0] & 0xfffffffc;
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}
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i825xx_dev->have_eeprom = i825xx_detect_eeprom();
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if (i825xx_dev->have_eeprom) {
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unsigned short temp;
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temp = net_eeprom_read(0);
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mac[0] = temp & 0xff;
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mac[1] = temp >> 8;
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temp = net_eeprom_read(1);
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mac[2] = temp & 0xff;
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mac[3] = temp >> 8;
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temp = net_eeprom_read(2);
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mac[4] = temp & 0xff;
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mac[5] = temp >> 8;
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} else {
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unsigned char *mem_base_mac_8 = (unsigned char *)(mem_base + 0x5400);
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unsigned int *mem_base_mac_32 = (unsigned int *)(mem_base + 0x5400);
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if (mem_base_mac_32[0] != 0) {
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for (int i = 0; i < 6; i++) {
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mac[i] = mem_base_mac_8[i];
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}
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} else {
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free(i825xx_dev);
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free(ether_dev);
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return (void *)0;
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}
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}
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char *pagesrx = mem_alloc_pages((NUM_RX_DESCRIPTORS * sizeof(struct i825xx_rx_desc_t) + 16) / PAGE_SIZE);
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unsigned char ptr = mem_pci_sbrk(NUM_RX_DESCRIPTORS * sizeof(struct i825xx_rx_desc_t) + 16);
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i825xx_dev->rx_buff = (struct i825xx_rx_desc_t *)ptr;
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for (i=0;i<(NUM_RX_DESCRIPTORS * sizeof(struct i825xx_rx_desc_t) + 16) / PAGE_SIZE;i++) {
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mem_map_page(pagesrx + (i * PAGE_SIZE), (char *)i825xx_dev->rx_desc + (i * PAGE_SIZE), 3);
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}
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for (i = 0; i < NUM_RX_DESCRIPTORS; i++) {
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i825xx_dev->rx_desc[i] = (struct i825xx_rx_desc_t *)((unsigned char *)i825xx_dev->rx_buff + i * 16);
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i825xx_dev->rx_desc[i]->address = (unsigned long long)(unsigned char *)(malloc(8192 + 16));
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i825xx_dev->rx_desc[i]->status = 0;
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}
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mmio_write(i825xx_dev, REG_TDBAL, (unsigned int)((unsigned long long)ptr >> 32));
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mmio_write(i825xx_dev, REG_TDBAH, (unsigned int)((unsigned long long)ptr & 0xFFFFFFFF));
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mmio_write(i825xx_dev, REG_RDBAL, (unsigned long long)ptr);
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mmio_write(i825xx_dev, REG_RDBAH, 0);
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mmio_write(i825xx_dev, REG_RDLEN, NUM_RX_DESCRIPTORS * 16);
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mmio_write(i825xx_dev, REG_RDH, 0);
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mmio_write(i825xx_dev, REG_RDT, NUM_RX_DESCRIPTORS - 1);
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i825xx_dev->rx_front = 0;
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mmio_write(i825xx_dev, REG_RCTRL, RCTL_SBP| RCTL_UPE | RCTL_MPE | RCTL_LBM_OFF | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
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pagesrx = mem_alloc_pages((NUM_TX_DESCRIPTORS * sizeof(struct i825xx_tx_desc_t) + 16) / PAGE_SIZE);
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ptr = mem_pci_sbrk(NUM_TX_DESCRIPTORS * sizeof(struct i825xx_tx_desc_t) + 16);
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i825xx_dev->tx_buff = (struct i825xx_tx_desc_t *)ptr;
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for(i = 0; i < NUM_TX_DESCRIPTORS; i++)
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{
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tx_descs[i] = (struct i825xx_tx_desc_t *)((unsigned char*)i825xx_dev->tx_buff + i*16);
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tx_descs[i]->addr = 0;
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tx_descs[i]->cmd = 0;
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tx_descs[i]->status = TX_DESC_STATUS_DD;
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}
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mmio_write(i825xx_dev, REG_TDBAH, (unsigned int)((unsigned long long)ptr >> 32) );
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mmio_write(i825xx_dev, REG_TDBAL, (unsigned int)((unsigned long long)ptr & 0xFFFFFFFF));
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//now setup total length of descriptors
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mmio_write(i825xx_dev, REG_TDLEN, NUM_TX_DESCRIPTORS * 16);
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//setup numbers
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mmio_write(i825xx_dev, REG_TDH, 0);
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mmio_write(i825xx_dev, REG_TDT, 0);
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i825xx_dev->tx_front = 0;
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mmio_write(i825xx_dev, REG_TCTRL, (15 << TCTL_CT_SHIFT)
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| (64 << TCTL_COLD_SHIFT)
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| TCTL_RTLC);
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// This line of code overrides the one before it but I left both to highlight that the previous one works with e1000 cards, but for the e1000e cards
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// you should set the TCTRL register as follows. For detailed description of each bit, please refer to the Intel Manual.
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// In the case of I217 and 82577LM packets will not be sent if the TCTRL is not configured using the following bits.
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mmio_write(i825xx_dev, REG_TCTRL, 0b0110000000000111111000011111010);
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mmio_write(i825xx_dev, REG_TIPG, 0x0060200A);
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if (!irq_install_handler(pci_dev->irq, i825xx_isr, 0)) {
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kprintf("Failed to install IRQ handler...\n");
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free(i825xx_dev);
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free(ether_dev);
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return (void *)0;
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}
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//enable all interrupts (and clear existing pending ones)
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mmio_write(i825xx_dev, REG_IMS, 0x1F6DC); //this could be 0xFFFFF but that sets some reserved bits
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mmio_read(i825xx_dev, REG_ICR);
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ether_dev->data = (char *)i825xx_dev;
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ether_dev->type = 1;
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ether_dev->state = 0;
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ether_dev->default_gw = 0;
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i825xx_dev->ether = ether_dev;
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kprintf("ETHER: Found i825xx Ethernet Controller MAC %x:%x:%x:%x:%x:%x IRQ %d\n", ether_dev->mac[0], ether_dev->mac[1], ether_dev->mac[2], ether_dev->mac[3], ether_dev->mac[4], ether_dev->mac[5], pci_dev->irq);
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return ether_dev;
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}
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void i825xx_enable(struct ether_t *ether) {
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struct i825xx_device_t *i825xx_device = (struct i825xx_device_t *)ether->data;
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mmio_write(i825xx_device, REG_TCTL, mmio_read(i825xx_device, REG_TCTL) | TCTL_EN | TCTL_PSP);
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mmio_write(i825xx_device, REG_RCTL, mmio_read(i825xx_device, REG_RCTL) | RCTL_EN);
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ether->state = mmio_read(i825xx_device, REG_STATUS) & STATUS_LU ? 1 : 0;
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}
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void i825xx_disable(struct ether_t *ether) {
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struct i825xx_device_t *i825xx_device = (struct i825xx_device_t *)ether->data;
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mmio_write(i825xx_device, REG_TCTL, mmio_read(i825xx_device, REG_TCTL) & ~(TCTL_EN | TCTL_PSP));
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mmio_write(i825xx_device, REG_RCTL, mmio_read(i825xx_device, REG_RCTL) & ~(RCTL_EN));
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ether->state = 0;
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}
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